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19-2125; Rev 1; 10/01
10-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface
General Description
The MAX5721 dual 10-bit, low-power, buffered voltageoutput, digital-to-analog converter (DAC) is packaged in a space-saving 8-pin MAX package (5mm 3mm). The wide supply voltage range of +2.7V to +5.5V and 112A supply current accommodate low-power and low-voltage applications. DAC outputs employ on-chip precision output amplifiers that swing Rail-to-Rail(R). The MAX5721's reference input accepts a voltage range from 0 to VDD. In power-down the reference input is high impedance, further reducing the system's total power consumption. The 20MHz, 3-wire SPITM, QSPITM, MICROWIRETM and DSP-compatible serial interface saves board space and reduces the complexity of opto- and transformerisolated applications. The MAX5721 on-chip power-on reset (POR) circuit resets the DAC outputs to zero and loads the output with a 100k resistor to ground. This provides additional safety for applications that drive valves or other transducers that need to be off on power-up. The MAX5721's software-controlled powerdown reduces supply current to less than 0.3A and provides software-selectable output loads (1k, 100k, or high impedance) while in power-down. The MAX5721 is specified over the -40C to +125C automotive temperature range o Ultra-Low Power Consumption 112A at VDD = +3.6V 135A at VDD = +5.5V o Wide +2.7V to +5.5V Single-Supply Range o Tiny 8-Pin MAX Package o 0.3A Power-Down Current o Guaranteed 10-Bit Monotonicity (1LSB DNL) o Safe Power-Up Reset to Zero Volts at DAC Output o Three Software Selectable Power-Down Impedances (100k, 1k, Hi-Z) o Fast 20MHz, 3-Wire SPI, QSPI, and MICROWIRECompatible Serial Interface o Rail-to-Rail Output Buffer Amplifiers o Schmitt-Triggered Logic Inputs for Direct Interface to Optocouplers o Wide -40C to +125C Operating Temperature Range
Features
MAX5721
Applications
Automatic Tuning Gain and Offset Adjustment Power Amplifier Control Process Control I/O Boards Battery-Powered Instruments VCO Control
TOP VIEW
Ordering Information
PART MAX5721EUA MAX5721AUA TEMP RANGE -40C to +85C -40C to +125C PIN-PACKAGE 8 MAX 8 MAX
Pin Configuration
Functional Diagram appears at end of data sheet. Rail-to-Rail is a registered trademark of Nippon Motorola, Inc. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor, Corp.
VDD 1 GND CS 2
8 7
OUTB OUTA REF DIN
MAX5721
3 6 5 SCLK 4
MAX
________________________________________________________________ Maxim Integrated Products
1
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10-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface MAX5721
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V OUT_, SCLK, DIN, CS, REF to GND...............-0.3 to (VDD+0.3V) Maximum Continuous Current Into Any Pin......................50mA Continuous Power Dissipation (TA = +70C) 8-Pin MAX (derate 4.6 mW/C above +70C) ............362mW Operating Temperature Range .........................-40C to +125C Junction Temperature .....................................................+150C Storage Temperature Range ............................-65C to +150C Lead Temperature (soldering, 10s) ................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5k, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are VDD = +5V, TA = +25C.)
PARAMETER STATIC ACCURACY (Note 1) Resolution Intergral Nonlinearity Error Differential Nonlinearity Error Zero-Code Error Zero-Code Error Tempco Gain Error Gain-Error Tempco Power-Supply Rejection Ratio REFERENCE INPUT Reference Input Voltage Range Reference Input Impedance Reference-Down Reference Current DAC OUTPUT Output Voltage Range DC Output Impedance Short-Circuit Current Wake-Up Time Output Leakage Current No load (Note 4) Code = 200 hex VDD = +3V VDD = +5V VDD = +3V VDD = +5V Power-down mode = output high impedance 0 0.8 15 48 8 8 18 VDD V mA s nA VREF RREF In operation In power-down mode In power-down mode (Note 3) 0 64 90 2 1 10 VDD 126 V k M A PSRR Code = 3FF hex, VDD = 10% GE Code = 3FF hex 0.26 58.8 N INL DNL OE (Note 2) Guaranteed monotonic (Note 2) Code = 000 0.4 2.3 3 10 0.5 4 1 1.5 Bits LSB LSB % of FS ppm/C % of FS ppm/C dB SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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10-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5k, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are VDD = +5V, TA = +25C.)
PARAMETER DIGITAL INPUTS (SCLK, DIN, CS) Input High Voltage Input Low Voltage Input Leakage Current Input Capacitance DYNAMIC PERFORMANCE Voltage-Output Slew Rate Voltage-Output Settling Time Digital Feedthrough Digital-Analog Glitch Inpulse DAC-to-DAC Crosstalk POWER REQUIREMENTS Supply Voltage Range Supply Current with No Load Power-Down Supply Current VDD IDD IDDPD All digital inputs at 0 or VDD = 3.6V All digital inputs at 0 or VDD = 5.5V All digital inputs at 0 or VDD = 5.5V 2.7 112 135 0.29 5.5 205 215 1 V A A SR 100 hex to 300 hex (Note 5) All digital inputs from 0 to VDD Major carry transition (code 1FF hex to code 200 hex) 0.5 4 0.1 12 10 V/s s nV-s nV-s nV-s VIH VIL IIN VDD = +3V, +5V VDD = +3V, +5V Digital inputs = 0 or VDD 0.1 5 0.7 x VDD 0.3 x VDD 1 V V A pF SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5721
TIMING CHARACTERISTICS
(VDD = 2.7V to 5.5V, GND = 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER SCLK Clock Frequency SCLK Pulse Width High SCLK Pulse Width Low CS Fall to SCLK Rise Setup Time SCLK Fall to CS Rise Setup Time DIN to SCLK Fall Setup Time DIN to SCLK Fall Hold Time CS Pulse Width High SYMBOL f SCLK tCH tCL tCSS tCSH tDS tDH tCSW CONDITIONS MIN 0 25 25 10 10 15 0 80 TYP MAX 20 UNITS MHz ns ns ns ns ns ns ns
Note 1: Note 2: Note 3: Note 4: Note 5:
DC specifications are tested without output loads. Linearity guaranteed from code 29 to code 995. Limited with test conditions. Offset and gain error limit the FSR. Guaranteed by design.
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10-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface MAX5721
__________________________________________Typical Operating Characteristics
(VREF = VDD, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. CODE, TA = +25C
MAX5721 toc01
DIFFERENTIAL NONLINEARITY vs. CODE, TA = +25C
0.20 0.15 0.10 DNL (LSB) 0.05 0 -0.05 -0.10 -0.15 -0.20 -0.25 -24 0 256 512 CODE 768 1024 0
MAX5721 toc02
TOTAL UNADJUSTED ERROR vs. CODE, TA = +25C
MAX5721 toc03
4 3 2 VDD = +3V INL (LSB) 1 0 -1 -2 -3 -4 0 256 512 CODE 768 VDD = +5V
0.25
1 TOTAL UNADJUSTED ERROR (%)
-4
-9
-14 VDD = +3V AND +5V -19
1024
256
512 CODE
768
1024
INTEGRAL NONLINEARITY vs. CODE, TA = +40C
MAX5721 toc04
DIFFERENTIAL NONLINEARITY vs. CODE, TA = -40C
MAX5721 toc05
TOTAL UNADJUSTED ERROR vs. CODE, TA = -40C
MAX5721 toc06
4 3 2 VDD = +5V
0.25 0.20 0.15 0.10 DNL (LSB) 0.05 0 -0.05 -0.10 -0.15 -0.20 -0.25
1 TOTAL UNADJUSTED ERROR (%)
-4
VDD = +3V AND +5V
INL (LSB)
1 0 -1 -2 -3 -4 0 256 512 CODE 768 1024 VDD = +3V
-9
-14
-19
-24 0 256 512 CODE 768 1024 0 256 512 CODE 768 1024
INTEGRAL NONLINEARITY vs. CODE, TA = +125C
MAX5721 toc07
DIFFERENTIAL NONLINEARITY vs. CODE, TA = +125C
0.20 0.15 0.10 DNL (LSB) 0.05 0 -0.05 -0.10 -0.15 -0.20 -0.25 -24 0 256 512 CODE 768 1024 0
MAX5721 toc08
TOTAL UNADJUSTED ERROR vs. CODE, TA = +125C
MAX5721 toc09
4 3 2 VDD = +3V INL (LSB) 1 0 -1 -2 -3 -4 0 256 512 CODE 768 VDD = +5V
0.25
1 TOTAL UNADJUSTED ERROR (%)
-4
VDD = +3V AND +5V
-9
-14
-19
1024
256
512 CODE
768
1024
4
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10-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface MAX5721
Typical Operating Characteristics (continued)
(VREF = VDD, TA = +25C, unless otherwise noted.)
WORST-CASE INL AND DNL vs. TEMPERATURE
MAX5721 toc10
SOURCE-AND-SINK CURRENT CAPABILITY (VDD = +3V)
MAX5721 toc11
SOURCE-AND-SINK CURRENT CAPABILITY (VDD = +5V)
4.5 4.0 3.5 VOUT (V) 3.0 2.5 2.0 1.5 1.0 CODE = 300 HEX, SOURCING CURRENT FROM OUT_ CODE = 100 HEX, SINKING CURRENT INTO OUT_ CODE = 000 SINKING CURRENT INTO OUT_ 0 2 4 6 8 10 12 14 16 CODE = 3FF HEX, SOURCING CURRENT FROM OUT_
MAX5721 toc12 MAX5721 toc15
4 3 2 INL AND DNL (LSB)
3.0 2.5 2.0 VOUT (V) 1.5 1.0 0.5 0 CODE = 300 HEX, SOURCING CURRENT FROM OUT_ CODE = 100 HEX, SINKING CURRENT INTO OUT_ CODE = 000 SINKING CURRENT INTO OUT_ 0 2 4 6 8 10 12 14 CODE = 3FF HEX, SOURCING CURRENT FROM OUT_
5.0
1 0 -1
MAXIMUM DNL
MAXIMUM INL
MINIMUM DNL -2 -3 -4 -40 -20 0 20 40
MINIMUM INL
0.5 0 16
60
80
100 120
TEMPERATURE (C)
ISOURCE/SINK (mA)
ISOURCE/SINK (mA)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5721 toc13
POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
POWER-DOWN SUPPLY CURRENT (nA)
MAX5721 toc14
SUPPLY CURRENT vs. CS INPUT VOLTAGE
900 800 SUPPLY CURRENT (A) 700 600 500 400 300 200 100 VDD = +3V VDD = +5V
160 140 SUPPLY CURRENT (A) 120 100 80 60 40 20 0 2.7 3.2 3.7 4.2 4.7 5.2 SUPPLY VOLTAGE (V) CODE = 3FF HEX
300 250 200 150 100 50 0 2.7 3.2 3.7 4.2 4.7 5.2 SUPPLY VOLTAGE (V)
0 0 1 2 3 4 5 CS INPUT VOLTAGE (V)
SUPPLY CURRENT vs. TEMPERATURE
MAX5721 toc16
FULL-SCALE SETTLING TIME (VDD = +5V)
MAX5721 toc17
FULL-SCALE SETTLING TIME (VDD = +5V)
MAX5721 toc18
160 140 SUPPLY CURRENT (A) 120 100 80 60 40 20 0 -40 -20 0 20 40 60 80 100 120 VDD = +3.6V VDD = +5.5V
VSCLK 5V/div
VSCLK 5V/div
VOUT_ 1V/div CODE 000 TO 3FF HEX RL = 5k CL = 200pF 1s/div CODE 3FF HEX TO 000 RL = 5k CL = 200pF 1s/div
VOUT_ 1V/div
TEMPERATURE (C)
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10-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface MAX5721
Typical Operating Characteristics (continued)
(VREF = VDD, TA = +25C, unless otherwise noted.)
HALF-SCALE SETTLING TIME (VDD = +3V)
MAX5721 toc19
HALF-SCALE SETTLING TIME (VDD = +3V)
MAX5721 toc20
VSCLK 5V/div
VSCLK 5V/div
VOUT_ 1V/div CODE 100 HEX TO 300 HEX RL = 5k CL = 200pF 1s/div CODE 300 HEX TO 100 HEX RL = 5k CL = 200pF 1s/div
VOUT_ 1V/div
EXITING POWER-DOWN (VDD = +5V)
MAX5721 toc21
DIGITAL-TO-ANALOG GLITCH IMPULSE (VDD = +5V)
VSCLK 5V/div
MAX5721 toc22
SCLK, fSCLK = 500kHz 2V/div
CODE 200 HEX
VOUT_ 1V/div
CODE 1FF HEX TO 200 HEX
VOUT_ AC-COUPLED, 20mV/div
5s/div
1s/div
DIGITAL-TO-ANALOG GLITCH IMPULSE (VDD = +3V)
MAX5721 toc23
DIGITAL-TO-ANALOG GLITCH IMPULSE (VDD = +5V)
SCLK, fSCLK = 500kHz, 2V/div
MAX5721 toc24
SCLK, fSCLK = 500kHz, 2V/div
CODE 1FF HEX TO 200 HEX
VOUT_ AC-COUPLED, 50mV/div CODE 200 HEX TO 1FF HEX 1s/div
VOUT_ AC-COUPLED, 50mV/div
1s/div
6
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10-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface MAX5721
Typical Operating Characteristics (continued)
( VREF = VDD, TA = +25C, unless otherwise noted.) DIGITAL-TO-ANALOG GLITCH IMPULSE (VDD = +3V) POWER-ON RESET, FAST RISE TIME (VDD = +5V)
SCLK, fSCLK = 500kHz, 1V/div
MAX5721 toc25
MAX5721 toc26
VDD 2V/div
CODE 200 HEX TO 1FF HEX 1s/div
VOUT_ AC-COUPLED, 20mV/div
VDD RISE TIME = 20s
VOUT_ AC-COUPLED, 10mV/div
20s/div
POWER-ON RESET, SLOW RISE TIME (VDD = +5V)
POWER-ON RESET, FAST RISE TIME (VDD = +3V)
VDD 2V/div VDD RISE TIME = 20s
MAX5721 toc27
MAX5721 toc28
VDD RISE TIME = 76s
VDD 2V/div
VOUT_ AC-COUPLED, 2mV/div
VOUT_ AC-COUPLED, 10mV/div
40s/div
20s/div
POWER-ON RESET, SLOW RISE TIME (VDD = +3V)
CLOCK FEEDTHROUGH (VDD = +5V)
MAX5721 toc30
MAX5721 toc29
VDD 2V/div VDD RISE TIME = 72s
SCLK, 2V/div
VOUT_ AC-COUPLED, 2mV/div
VOUT_, AC-COUPLED 1mV/div
40s/div
100ns/div fSCLK = 1MHz
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10-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface MAX5721
Typical Operating Characteristics (continued)
( VREF = VDD, TA = +25C, unless otherwise noted.)
LINE TRANSIENT RESPONSE (VDD = +5V)
CLOCK FEEDTHROUGH (VDD = +3V)
MAX5721 toc31
MAX5721 toc32
SCLK, 2V/div
VDD, AC-COUPLED, 100mV/div
VOUT_, AC-COUPLED 1mV/div
VOUT_ AC-COUPLED, 10mV/div
100ns/div fSCLK = 1MHz
20s/div
LINE TRANSIENT RESPONSE (VDD = +3V)
CROSSTALK (VDD = +5V)
MAX5721 toc34
MAX5721 toc33
VDD, AC-COUPLED, 100mV/div
VOUTA, 2V/div CODE 2FF HEX TO 008 HEX
VOUT_ AC-COUPLED, 10mV/div
VOUTB, AC-COUPLED 1mV/div
20s/div
4s/div
Pin Description
PIN 1 2 3 4 5 6 7, 8 NAME VDD GND CS SCLK DIN REF OUTA, OUTB Power-Supply Input Ground Chip-Select Input Serial Clock Input Serial Data Input External Reference Voltage Input DAC Voltage Outputs. Power-on reset sets DAC registers to zero, and internally connects OUT to GND with 100k resistor. FUNCTION
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10-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface
Detailed Description
The MAX5721 contains two 10-bit, voltage-output, lowpower digital-to-analog converters (DACs). Each DAC employs a resistor string architecture that converts a 10-bit digital input word to an equivalent analog output voltage proportional to the applied reference voltage. The MAX5721 shares one reference input (REF) between both DACs. The MAX5721 includes rail-to-rail output buffer amplifiers for each DAC, and input logic for simple microprocessor (P), and CMOS interfaces. The power-supply range is from +2.7V to +5.5V (Functional Diagram). The MAX5721's reference input accepts a voltage range from 0 to VDD. In power-down mode the reference input is high impedance. The MAX5721 is compatible with the 3-wire SPI, QSPI, MICROWIRE, and DSP serial interface with Schmitt-triggered logic inputs. the values contained in the registers when brought out of power-down. The recovery time, from total powerdown to power-up, is 8s. This extra time is needed to allow the internal bias to wake-up. Power-down mode reduces current consumption to 0.5A.
MAX5721
3-Wire Serial Interface
The MAX5721 digital interface is a standard 3-wire connection compatible with SPI/QSPI/MICROWIRE/DSP interfaces. The chip-select input (CS) frames the serial data loading at DIN. Immediately following CS high-tolow transition, the data is shifted synchronously and latched into the input register on the falling edge of the serial clock input (SCLK). After 16 bits have been loaded into the serial input register, it transfers its contents to the DAC latch. CS may then either be held low or brought high. CS must be brought high for a minimum of 80ns before the next write sequence, since a write sequence is initiated on a falling edge of CS. Not keeping CS low during the first 15 SCLK cycles discards input data. The serial clock (SCLK) can idle either high or low between transitions. Table 2 lists serial-interface programming commands.
Reference Input and DAC Output Range
The reference input accepts positive DC and AC signals. The voltage at REF sets the full-scale output voltage of both DACs. The reference input voltage range is 0 to VDD. The impedance at REF is 90k. The voltage at REF can vary from GND to VDD. The output voltages (VOUT_) are represented by a digitally programmable voltage source as: VOUT_ = (VREF D) / 210 where D is the decimal equivalent of binary DAC input code ranging from 0 to 1023. VREF is the voltage at REF.
Power-On Reset (POR)
The MAX5721 has an internal POR circuit. At power-up all DACs are powered-down and OUT_ is terminated to GND through 100k resistors. Contents of input and DAC registers are cleared to all zero. An 8s recovery time after issuing a wake-up command is needed before writing to the DAC registers. Power-down mode control commands can be applied immediately with no recovery time. C3-C0 are control bits. The data bits D9 to D0 are in straight binary format. Set bits S1 and S0 to zero. All zeros correspond to zero scale and all ones correspond to full scale.
Output Buffer Amplifiers
All DACs are internally buffered at the output. The buffer amplifiers have both rail-to-rail common mode and (GND to VREF) output voltage range. The buffers are unity-gain stable with CL = 200pF and RL = 5k. Buffer amplifiers are disabled during power-up and individual DAC outputs are shorted to GND through a 100k resistor. Buffer amplifiers can individually or altogether be powered-down by programming the input register control bits. During power down, contents of the input and DAC registers remain the same. On wake-up all DAC outputs are restored to their prepower-down voltage values.
Digital Inputs
The digital inputs are compatible with CMOS logic. In order to save power and reduce input to output coupling, SCLK and DIN input buffers are powered down immediately after completion of shifting 16 bits into the input shift register. A high to low transition at CS powers up SCLK and DIN input buffers.
Applications Information
Unipolar Output
The typical application circuit (Figure 3) shows the MAX5721 configured for a unipolar output, where the output voltages and the reference inputs have the same polarity. Table 3 lists the unipolar output codes.
Power-Down Mode
In power-down mode, the DAC outputs are programmed to one of three output states, 1k, 100k, or floating (Table 1). The REF input is high impedance (2M typ) to conserve current drain from the system reference; therefore, the system reference does not have to be powered-down. The DAC outputs return to
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10-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface MAX5721
Table 1. Power-Down Mode Control
EXTENDED CONTROL C3 1 1 1 1 1 1 1 1 1 1 1 1 C2 1 1 1 1 1 1 1 1 1 1 1 1 C1 1 1 1 1 1 1 1 1 1 1 1 1 C0 1 1 1 1 1 1 1 1 1 1 1 1 D9-D3 X X X X X X X X X X X X D2 0 0 0 0 0 0 0 0 1 1 1 1 DATA BITS D1 0 0 0 0 0 0 0 0 0 0 0 0 D0 0 0 0 0 1 1 1 1 0 0 0 0 S1 0 0 1 1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 0 1 0 1 DAC A DAC A DAC A DAC A DAC B DAC B DAC B DAC B DAC A-B DAC A-B DAC A-B DAC A-B DAC O/P, wake-up Floating output Output is terminated with 1k Output is terminated with 100k DAC O/P, wake-up Floating output Output is terminated with 1k Output is terminated with 100k DAC O/P, wake-up Floating output Output is terminated with 1k Output is terminated with 100k DESCRIPTION FUNCTION
X = Don't Care
CONTENTS OF INPUT SHIFT REGISTER D15 (MSB) C3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D0 (LSB) S1 S0
Figure 1. 16-Bit Input Word
tCH
SCLK tCL tCSW tCSS tDS CS tDH tCSH
DIN
C3
SO
Figure 2. Timing Diagram
10
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10-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface MAX5721
Table 2. Serial-Interface Programming Commands
CONTROL C3 0 0 0 0 1 1 1 1 1 C2 0 0 1 1 0 0 1 1 1 C1 0 0 0 0 0 0 0 0 1 C0 0 1 0 1 0 1 0 1 0 DATA BITS D9-D0 X X X X X X X X X S1-S0 X X X X X X X X X DAC A B A B A B A-B A-B A-B FUNCTION Shift reg through DAC reg, O/P updated Shift reg through DAC reg, O/P updated Shift reg through I/P reg, O/P unchanged Shift reg through I/P reg, O/P unchanged I/P reg through DAC reg, O/P updated I/P reg through DAC reg, O/P updated Shift reg through DAC reg, O/P updated Shift reg through I/P reg, O/P unchanged I/P reg through DAC reg, O/P updated
X = Don't Care
Bipolar Output
The MAX5721 can be configured for bipolar operation using a dual supply op amp (Figure 4). The transfer function for bipolar operation is: 2D VOUT = VREF - 1 1024 where DB is the decimal value of the DACs binary input code. Table 4 shows digital codes (offset binary) and corresponding output voltages for the circuit in Figure 4.
Power Supply and Layout Considerations
Careful PC board layout is important for optimal system performance. To reduce noise injection and digital feedthrough, keep analog and digital signals separate. Ensure that that the return path from GND to the supply ground is short and low impedance. Use a ground plane. Bypass VDD to GND with a 0.1F capacitor as close as possible to VDD.
+2.7V to +5.5V
R1
R2 V+
+2.7V to +5.5V
REF IN OUT DAC_
VDD OUT_ DAC_
REF
VDD OUT_
VOUT
MAX6050
GND GND V-
MAX5721
GND
MAX5721
R1 = R2
Figure 3. Typical Operating Circuit, Unipolar Output
Figure 4. Bipolar Output Circuit
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10-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface MAX5721
Table 3. Unipolar Code Table
DAC CONTENTS 1111 1111 1100 ANALOG OUTPUT
Table 4. Bipolar Code Table
DAC CONTENTS 1111 1111 1100 ANALOG OUTPUT
1023 + VREF 1024 513 + VREF 1024 V + REF 2 511 + VREF 1024 1 + VREF 1024
0
511 + VREF 512 1 + VREF 512
0
-VREF
1000 0000 0100
1000 0000 01000 1000 0000 0000
1000 0000 0000
0111 1111 11100
1 512 511 512
0111 1111 1100
0000 0000 0100 0000 0000 0000
-VREF
0000 0000 0100 0000 0000 0000
-VREF
Chip Information
TRANSISTOR COUNT: 7737 PROCESS: BiCMOS
12
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10-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface
Functional Diagram
VDD REF
MAX5721
INPUT AND DAC REGISTER
10-BIT DAC
OUTPUT BUFFER
OUTA
RESISTOR NETWORK
INPUT AND DAC REGISTER
10-BIT DAC
OUTPUT BUFFER
OUTB
INPUT CONTROL LOGIC AND SHIFT REGISTER
RESISTOR NETWORK POWER-DOWN CONTROL LOGIC
MAX5721
CS
SCLK
DIN
GND
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13
10-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface
Package Information
8LUMAXD.EPS
MAX5721
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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